1. Field of the Invention
The present invention generally relates to a method for forming dielectric isolation regions in a semiconductor substrate, and more particularly to an improved method for forming an air-filled isolation trench in a silicon substrate.
2. Description of the Prior Art
So-called trenches are commonly used in the fabrication of semiconductor devices to isolate active regions of the semiconductor substrate. Usually, the isolating trench is filled with a dielectric material. Polysilicon, chemically vapor deposited (CVD) silicon dioxide, BSG glass, and polyimides are examples of prior art trench-fill materials. Each of these materials have a dielectric constant which is considerably larger than that of air. As will be appreciated by those skilled in the art, an air-filled trench would be advantageous in that it would minimize the parasitic coupling between devices isolated by the trench and reduce electrical leakage and mechanical stress as compared with trench-fill materials of the type described above.
Proposals have been made in the prior art for an air-filled isolation trench.
U.S. Pat. No. 4,169,000 discloses a method for forming a fully-enclosed air isolation structure which comprises etching a pattern of cavities extending from one surface of a silicon substrate into the substrate to laterally surround and electrically isolate the substrate pockets. Prior to etching a cavity pattern, a first layer of silicon dioxide is formed on the substrate surface. A planar layer of silicon dioxide is formed on a separate silicon substrate which is then placed over the first substrate to cover the openings. This latter planar layer of silicon dioxide is fused to the silicon dioxide in the substrate having patterns of cavities formed therein. The separate silicon substrate is removed leaving cavities fully enclosed by the silicon dioxide layer.
U.S. Pat. No. 4,356,211 discloses dielectric isolation trenches in a monocrystalline silicon substrate by reactive ion etching after having etched openings in a layered structure of silicon dioxide and silicon nitride on the surface of the substrate. The walls of the trenches in the substrate are oxidized prior to depositing polycrystalline silicon on the substantially vertical side walls of the trenches in the substrate and on the substantially vertical walls defining the openings in the layered structure. The top portion of the polycrystalline silicon on the substantially vertical walls of the openings in the layered structure is selectively doped so that the polycrystalline silicon on the top portion of the vertical walls of the openings in the layered structure will oxidize at least twice as fast as the polycrystalline silicon on lower part of the side walls of the trenches in the substrate. Thermal oxidation causes the polycrystalline silicon to close the upper end of each of the trenches while leaving an air space therebeneath to form the dielectric isolation regions.
U.S. Pat. No. 4,888,300 discloses a trench cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitaxial layer surrounded by the trench by means of an oxide bridge, the underlying region of the buried layer is etched away to form a cavity under the active area. This cavity, as well as the surrounding trench, is then filled with a suitable insulating material to isolate the active island from the substrate.
U.S. Pat. No. 4,916,513 discloses an integrated circuit structure which is made up of laterally-spaced islands separated from each other by closed annular grooves of an electrically isolating matter which can be either ambient air or vacuum, or an oxide formed from the adjacent semiconductor material.
Japanese patent number 60,147131 dated Mar. 8, 1985 discloses dielectric isolating grooves formed downward from the surface of an Si substrate. An SiO.sub.2 film is formed in the groove by means of CVD.